1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of forming landing pads.
2. Description of the Related Art
Currently, the line width of the semiconductor fabrication process is already at the sub-micron level. Reducing the line width of the fabrication process is an approach to improve the efficiency of a semiconductor device, and reduce the fabrication cost as well. Downsizing a semiconductor device can be partially accomplished by improving the resolution of some fabrication processes, such as photolithography dry etching processes. More advanced exposure equipment and more sensitive photo-resists are certainly required for a sub-micron photolithography process.
Additionally, more precise and advanced etching equipment and methods are also used for more correctly and successfully transferring patterns. Although developing advanced equipment and methods help to downsize a semiconductor device, the task is still mainly dependent on minimizing the structure of a semiconductor device.
For example, in order to reduce the size of a semiconductor device, a conducting structure that is used to connect a bit line or a node in an upper layer of the source/drain regions of a transistor of a lower layer, has to be reduced in size. Methods according to the foregoing goal have been developed and used, wherein the methods include placing a narrow polysilicon plug between the bit line and the source/drain regions underneath. However, forming a narrow polysilicon plug on the source/drain regions and then forming a bit line over the polysilicon plug requires very precise photolithography processes that are difficult to accomplish when line width is at the sub-micron level.
FIGS. 1A to 1E are cross-sectional views of a semiconductor device showing a conventional structure of landing pads.
FIG. 1A shows a substrate 100 which contains a transistor 108 consisting of a gate 102, an insulating layer 104 and a spacer 106. A first dielectric layer 110, such as a silicon dioxide layer is formed over entire substrate 100.
FIG. 1B illustrates definition of the first dielectric layer 110 by a photolithography process. A contact opening (not shown) is formed in the first dielectric layer 110 by etching to expose the substrate 100. Then, a first conductive layer 112 is formed over the first dielectric layer 110 and fills the contact opening.
Next, as illustrated in FIG. 1C, the first conductive layer 112 is partially removed to expose the surface of the first dielectric layer 110 and to form landing pads 113 which have a top surface lower than the first dielectric layer 110 in the contact opening. The step is performed by etching back the conductive layer 112.
FIG. 1D illustrates formation of a second dielectric layer 114, such as a silicon dioxide layer, over the first dielectric layer 110 and the landing pads 113.
FIG. 1E illustrates definition of the second dielectric layer 114, which is then partially removed to form a via 116 in it and to expose one of the landing pads 113. A second conductive layer (not shown) is formed over the second dielectric layer 114 and defined to form a bit line 118 coupling with the exposed landing pad 113 through the via 116.
The landing pad patterns are separated by a certain distance. Downsizing a semiconductor device is limited by photolithography resolution. Since the distance between landing pads generally cannot be shorter than 0.22 .mu.m, the size of a landing pad is limited and generally cannot be increased. The limit of the landing pad size makes the more difficult.
Furthermore, some of the landing pads 113 connecting to the substrate 100 are used as bit lines, and other landing pads 113 are used as nodes and are connected to conductors during back-ending processes. Forming the nodes comprises a step of depositing a third dielectric layer over the bit lines and a step of using a photolithography process to form vias as node contacts to the other landing pads through the second and the third dielectric layer.
It will be appreciated that the structure formed by the method described above is relatively high, and the node contact vias must be formed standing off the first and the second conductive layers. This makes the process more difficult. On the other hand, masks used to form vias must have a higher alignment during photolithography processes. This means that those processes have a poor tolerance of alignment deviation.